Reliability of probabilistic circuits

Overview & Synopsis

The Moore’s Law has benefited us a lot since 1970s. As conceptualized by R. Dennard [1], one can obtain transistors with higher speed and lower energy consumption in reducing the critical dimensions and keeping the electrical field constant. This concept made the continuous trend of increase in integration density of CMOS (Complementary MetalOxide- Silicon) technology possible. Since 1970s, the number of components per chip has doubled every two years [2]. As mentioned in the ITRS (International Technology Roadmap for Semiconductors) 2007 [3], the operation frequency of a transistor will reach 12 GHz and the number of transistors contained in a single chip may be 12 billion in 2020. With the dimension shrinking to nanometer, or Deep Submicron Meter (DSM), many challenges have risen, one of which is the dramatically increasing probability of soft errors induced by Single Event Upsets (SEUs) or Single Event Transients (SETs). Normally, these kinds of soft errors often happened in the memory cells and rarely occurred in the logic circuits on the ground level. However, the increased operation frequency, the lower supply voltage and the reduced noise margin have made the transient current pulses induced by alpha particles or high-energy neutrons much easier to be captured by the filp-flops at the outputs of logic circuits. Consequently, the reliability of logic circuits (including the evaluation methodologies) in nanometer regime have been an important design criterion in ICs design [4]. Another challenge accompany with the CMOS dimension scaling to nanometer is that the thermal noise is not neglectable any more. As pointed in [2], the RMS of thermal noise will increase during miniaturization. The probability of the thermal noise crossing the voltage threshold also steadily increases with the reduction of the noise margin [2]. Thus the noise-immunity of logic circuits is also an important concern in ICs designs. Therefore, with CMOS technology scaling into DSM or nanometers, the behaviour of logic gates, the output of logic functions or even the services of systems are not determin- istic but probabilistic. The reliability of probabilistic circuits, induced by the soft errors and noise, draws much more attention in modern IC designs. This thesis concentrates on the reliability evaluation methodology improvements and the general cost-effective noise-tolerant circuit designs. An efficient evaluation methodology based on Probability Transfer Matrix (PTM) is proposed to obtain the accurate reliability of a combinational circuit. Compared with the traditional PTM, the proposed PTM (denoted as ECPTM) can dramatically reduce the penalty in time consumption and memory usage. A general analytic tool has been developed to get the reliability of a circuit with its netlist file. The efficiency improvement of the proposed method is verified with practical bench circuits. This thesis also presents a general cost-effective noise-immune design structure of logic functions. This design structure is based on Markov Random Fields (MRF) and is suitable for all the basic logic gates as well as complex logic functions involving several logic gates. This structure has been verified through simulations done in SPICE using the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5] and in Spectre based on ST 65nm CMOS models. Furthermore, this thesis proposes a model to analyze the reliability issues induced by both SETs and noise. Mathematical conditions are derived in order to improve the SETs robustness and noise-immunity at the same time.