High Level Power Estimation for DSP

Overview & Synopsis

We present here a high level power estimation method for Digital Signal Processor (DSP) based on an original functional analysis together with practical validations. Instead of classical methods conducted at instruction level, we evaluate the power consumption of a whole algorithm at a behavioural level; first are extracted for the given algorithm characteristics such as parallelism rate, cache miss rate, memory mode... and then these parameters are applied to empirical consumption laws. As example, the energy model elaborated for a TEXAS INSTRUMENTS DSP is provided; our method applied to classical algorithm (FIR ) has also been validated by measurements.