Probabilistic Computing with Neuromorphic Elements

Overview & Synopsis

This paper presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130 nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood functions are directly embedded in the parameters of synapse-like analog circuits. Posterior probabilities are obtained through temporal interactions between these signals using simple circuit primitives, notably an analog coincidence detection or a Muller C-element. The final decision is determined using a time-to-first-spike encoding scheme. In contrast to prior hardware implementations that rely on stochastic sampling, memory-based representations, or explicit evaluation of probabilistic graphs, the proposed approach performs inference through the continuous-time dynamics of a statically configured analog circuit. This avoids random-number generation for probability-stream generation, explicit memory access and analog-to-digital conversion during inference. The approach is validated through circuit-level simulations on a breast cancer classification task, achieving accuracies of 73–90%, comparable to software implementations, while operating in the μW power range. These results demonstrate a compact and energy-efficient solution for low-dimensional probabilistic inference, particularly suited for near-sensor and edge computing applications.