Intertrack surface losses in miniature coplanar waveguide on silicon-on-insulator

Overview & Synopsis

Attenuation has been studied in different-sized coplanar waveguides (CPW) patterned onto silicon-on-insulator (SOI) for three different surfaces between the CPW tracks: a silicon dioxide/silicon interface, a hydrogen-terminated silicon surface, and a native oxide. For large-gap CPW (signal track width $s$ = 100 µm, gap width $g$ = 63.5 µm), selective removal of the silicon dioxide from between the metal tracks reduces losses from 0.79 dB mm−1 to 0.69 dB mm−1 at 50 GHz. The subsequent growth of a native oxide on the silicon surface between the tracks results in losses equal to 0.67 dB mm−1. For small-gap CPW ($s$ = 2 µm, $g$ = 2.5 µm), losses are reduced from 5.6 dB mm−1 to 3.4 dB mm−1 at 50 GHz by selectively removing the silicon oxide between the metal tracks. However, when a native oxide is allowed to grow on the silicon surface between the tracks, the losses increase significantly to 5.8 dB mm−1. When the native oxide is removed, the losses decrease to those observed following removal of the silicon dioxide. The measurements suggest that the contribution of the intertrack surface losses is the result of free-carrier losses due to a surface inversion layer. The surface-associated losses are proportionally larger as the CPW dimensions shrink—as predicted by modelling. We suggest that technologies employing miniature CPW should take this into account. The native oxide should be routinely removed if possible—implying that appropriate chemically-resistant metallisation be chosen, or fabrication processes should incorporate stable passivation of silicon surfaces between CPW tracks to avoid native oxide growth. Conversely, the increased sensitivity of attenuation to surface effects by shrinking CPW dimensions suggests that CPW-based sensors could benefit from miniaturization.