An IR-Drop Simulation Principle Oriented to Delay Testing
Overview & Synopsis
This paper deals with delay fault simulation of logic circuits in the context of IR-drop induced delay. An original algorithm is proposed allowing to perform a per-cycle delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).
Indexed from repository: HAL Open Science
(
hal.science)
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Document Information
| Document Title | An IR-Drop Simulation Principle Oriented to Delay Testing |
|---|---|
| Author / Organization | Marina Aparicio Rodriguez, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker |
| Subject & Discipline | Multidisciplinary Academic Open Research |
| Categories | Science & Mathematics |
| Publication Year | 2012 |
| License / Rights | Open Access / Creative Commons |
| Resource Verification | Listed PDF (Verification Pending) |
| Original Host Website |
HAL Open Science
(hal.science)
|
| File Format | application/pdf (Portable Document Format) |
| Language | EN |
| Catalog ID | DOC-193204 |
| Original Source Link | Visit Source Page on hal.science » |