Hardware Architectures for HECC

Overview & Synopsis

Recent research has pointed out Hyper-Elliptic Curve Cryptography (HECC) as an attractive alternative to ECC in public-key cryptography. HECC is based on a different kind of curves, which allows the size of the field elements to be halved, but at the expense of an increased number of finite field operations. HECC internal parallelism brings forward numerous questions for hardware implementation. In this work, we present arithmetic operators and implementations of hardware accelerators for HECC. We first improved the hardware utilization of the multiplier unit with new solution named hyper-threaded modular multiplier which fills the unused stages of the DSP blocks with other independent modular multiplications. Then, we explore various architectures for our HECC accelerator, starting from a classical Harvard architecture and changing architectural parameters, such as the numbers and types of arithmetic units.