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Memory Authenticated Encryption Eengine for a RISC-V processor
Karim Ait Lahssaine, Olivier Savry

Memory Authenticated Encryption Eengine for a RISC-V processor

Author / Organization:
Science & Mathematics Published 2023 Verification Pending

Overview & Synopsis

In this paper, we present the Memory Authenticated Encryption Engine (MAEE) hardware countermeasure to ensure the confidentiality and authenticity of data in RAM and the associated interconnect bus. Using the Subterranean 2.0 authenticated encryption algorithm, data used by a processor is secured at the output of cache memory, and stored in memory as chunks, containing encrypted data and metadata for authenticity verification. The MAEE provides protection against attacks targeting the memory and its bus, such as Rowhammer, fault injections or side-channel attacks. We are also evaluating the performance of this countermeasure, by associating it with the RISC-V CVA6 application core.

Indexed from repository: HAL Open Science (hal.science)
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Document Information

Document Title Memory Authenticated Encryption Eengine for a RISC-V processor
Author / Organization Karim Ait Lahssaine, Olivier Savry
Subject & Discipline Multidisciplinary Academic Open Research
Categories Science & Mathematics
Publication Year 2023
License / Rights Open Access / Creative Commons
Resource Verification Listed PDF (Verification Pending)
Original Host Website HAL Open Science (hal.science)
File Format application/pdf (Portable Document Format)
Language EN
Catalog ID DOC-171789
Original Source Link Visit Source Page on hal.science »