Evaluation of Design for Reliability Techniques in Embedded Flash Memories
Overview & Synopsis
Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floatinggate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems ; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs use techniques such as Error Correction Code (ECC), Redundancy or Threshold Voltage (VT) Analysis. In this paper, a memory model to evaluate the reliability of eFlash memory arrays under distinct enhancement schemes is developed.
Indexed from repository: HAL Open Science
(
hal.science)
Keyboard Shortcuts:
← / → for pages • + / - for zoom • 0 to fit width
Powered by Mozilla PDF.js v3.11
Document Information
| Document Title | Evaluation of Design for Reliability Techniques in Embedded Flash Memories |
|---|---|
| Author / Organization | Benoît Godard, Jean-Michel Daga, Lionel Torres, Gilles Sassatelli |
| Subject & Discipline | Multidisciplinary Academic Open Research |
| Categories | Science & Mathematics |
| Publication Year | 2007 |
| License / Rights | Open Access / Creative Commons |
| Resource Verification | Listed PDF (Verification Pending) |
| Original Host Website |
HAL Open Science
(hal.science)
|
| File Format | application/pdf (Portable Document Format) |
| Language | EN |
| Catalog ID | DOC-16645 |
| Original Source Link | Visit Source Page on hal.science » |