PARIS: Parallel Arithmetic Reduction and Integrated Selection for MSDF Inner Products

Overview & Synopsis

Existing most-significant-digit-first (MSDF) accelerators serialize input-term processing, causing inner-product latency to increase with fan-in. This paper presents PARIS, an MSDF architecture that eliminates input-term serialization through parallel bit-plane reduction and shared carry-save residual selection. For $B$-bit operands, PARIS processes $B^2$ bit-position pairs, independent of fan-in within the supported tile, while generating exact MSDF outputs. Synthesized in 45\,nm at 100\,MHz, the 784-lane INT8 core occupies 0.008701\,mm$^2$ and completes an inner product in 88 cycles. Evaluation on two MNIST multilayer perceptrons demonstrates arithmetic-workload speedups of 240.44$\times$ and 180.47$\times$ over a matched reused-MSDF implementation, reducing arithmetic energy by 98.89\% and 98.58\%, respectively. A synthesized 16-engine accelerator occupies 0.90273\,mm$^2$ and meets the 100\,MHz timing constraint. Assuming immediate weight availability, it delivers a projected throughput of 24.33\,GOPS and an estimated energy efficiency of 1,581.14\,GOPS/W at unchanged mapped power. Bias-aware ReLU detection further reduces modeled arithmetic cycles by 5.52\% and 4.86\%. A separate 256-engine RTL implementation completes Model A in 259 cycles, demonstrating output-parallel scalability.