An Energy-Efficient Wideband Input-Buffer for High-Speed CMOS ADCs

Overview & Synopsis

Input buffers (IBs) for driving analog-to-digital converters (ADCs) in direct down-conversion radio frontends are normally operated with supply voltages higher than the nominal, mainly due to bandwidth (BW) and dynamic linearity constraints. Therefore, several voltage-regulators are required as well as the need of having I/O devices capable of handling such voltages. An energy-efficient input buffer architecture is presented in this paper and fairly compared to other existing IB realizations using a standard 1.2-V 130-nm CMOS technology as reference. The proposed new architecture presents better dynamic performance, and it can be readily used to drive moderate-resolution ADCs without requiring either a higher supply voltage or any non-standard I/O devices.