Memory repair architectures for high defect densities

Overview & Synopsis

Nanometric scaling increases the sensitivity of integrated circuits to defects andperturbations. Thus, each new generation of manufacturing process is accompanied by a rapiddegradation of manufacturing yield and reliability. Embedded memories occupy the largestpart of the area of SoCs and comprise the vast majority of transistors. In addition, forincreasing the integration density, they are designed very tightly to the design and electricalrules. Hence, embedded memories concentrate the majority of the manufacturing defectsaffecting a SoC, and are also more sensitive to perturbations. Thus, they are the parts of theSoC the most affected by the deterioration of manufacturing yield and reliability. This thesisdevelops repair architectures optimally combining test algorithms, BIST architectures, anderror correcting codes, in order to propose effective solutions for improving themanufacturing yield and reliability of embedded memories affected by high defect densities.