Transistor Level Layout of Integrated Circuits
Overview & Synopsis
This
note covers the following topics: Graph Theory, Chips, Linear Gate
Arrays, Two-Dimensional Gate Matrix, Transistor Row Placement, Cell Placement,
Routing, Evaluation of BONNCELL Features.
Indexed from repository: FreeBookCentre
(
freebookcentre.net)
Document Information
| Document Title | Transistor Level Layout of Integrated Circuits |
|---|---|
| Author / Organization | University of Bonn |
| Categories | Transistor Circuits |
| Resource Verification | Listed PDF (Verification Pending) |
| Original Host Website |
FreeBookCentre
(freebookcentre.net)
|
| File Format | application/pdf (Portable Document Format) |
| Page Count | 162 pages |
| Language | EN |
| Catalog ID | DOC-309629 |
| Original Source Link | Visit Source Page on freebookcentre.net » |